All of the material in this patent application is subject to copyright protection under the copyright laws of the United States and of other countries. As of the first effective filing date of the present application, this material is protected as unpublished material.
However, permission to copy this material is hereby granted to the extent that the copyright owner has no objection to the facsimile reproduction by anyone of the patent documentation or patent disclosure, as it appears in the United States Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
The present invention relates generally to the regulation and/or switching of voltage and/or current and/or power as applied to integrated circuits.
The basic problem addressed by the present invention can be best illustrated by reference to the block diagram of FIG. 1. Here it can be seen that a non-ideal voltage source (0101) is used to provide a current (IVS) to a complex load (0103) through a voltage/current/power regulator/switch (VCPRS) module (0102). It is important to note that the same non-ideal voltage source (0101) may simultaneously supply a variety of other loads (0106) through other VCPRS modules (0105) within the context of the entire system environment. The ground reference (0104) for the entire system is typically common but need not necessarily be so in all circumstances.
The primary function in many system contexts is for the voltage/current/power regulator module (0102) to regulate the output voltage supplied to the complex load (0103) so that it is constant under all loading conditions and also under all conditions of the non-ideal voltage source (0101). While the typical context of this regulation scheme is one of constant output voltage, there are applications in which a constant output current (or constant output power) are desired, and this discussion applies equally well to these environments.
Typically the voltage transformation from the non-ideal voltage source (0101) to the complex load (0103) can occur via dissipation in the VCPRS module (0102) (linear voltage regulation), or may occur within the context of a buck/boost voltage converter in which the voltage regulator/switch acts more strictly as a power converter with regulated output voltage and/or current. Neither configuration limits the teachings of the present invention, as the form of voltage/current regulation in both cases requires some common circuit elements that are the subject of the teachings herein. Therefore, it is sufficient to realize that the regulator function served by the VCPRS function (0102) is one of meeting the demands (voltage, current, power) to the load based on a specified regulation scheme.
As an example, the typical voltage regulation requirements for a modern microprocessor range from xc2x110% to xc2x15%, which for a 1.5V core voltage means a xc2x1150 mV to xc2x175 mV regulation range. This is in stark contrast to the xc2x1500 mV regulation range typically permitted for older 5V digital logic systems. A significant reason for limiting the regulation drift of a microprocessor power supply voltage (VDD) is one of reliability. As the gate oxide thickness of modern CMOS processes are reduced, the susceptibility to oxide punchthrough is increased and thus regulation of the power supply becomes a paramount reliability consideration.
The issue of voltage regulation is tightly related to another concept termed voltage dropout. As stated in the literature:
xe2x80x9cThe dropout voltage is the voltage at which the input voltage is low enough to cause the output to go out of regulation. With the reduction of logic voltages, the dropout voltage becomes more critical. A case in point in when you want a 1.5V alkaline cell to power a 1-V DSP. The alkaline cell can degrade to 1-V and the regulator can still provide power to within a few millivolts of 1 V. Dropout requirements dictate the type of pass element used and favor CMOS for very low-dropout regulators. Some regulators use a pass element and a low-loss switch that directly couples V(in) to V(out) with a small voltage drop across the switch.xe2x80x9d
See Brian Erisman, xe2x80x9cVoltage Regulation Tames Transientsxe2x80x9d and xe2x80x9cVoltage Regulation Takes Trade-Offsxe2x80x9d, ELECTRONIC ENGINEERING TIMES, at 84-100 (Oct. 4, 1999).
Note that the prior art clearly indicates that as supply voltages drop, the efficiency of the pass element becomes a significant design issue. However, little if any guidance is provided as to how to solve the problems associated with lowered supply voltages and fixed dropout voltage values in regards to high current or mixed signal integrated circuit systems.
While voltage regulation and switching are the primary focus of the present invention, current and/or power regulation may be equally implemented utilizing the disclosed invention teachings in conjunction with the prior art. Current regulators, of all power variations, are detailed in the literature. See Henri J. Oguey and Daniel Aebischer, xe2x80x9cCMOS Current Reference Without Resistancexe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 32, No. 7, at 1132-1135 (Jul, 1997).
Additionally, in many circumstances the VCPRS module (0102) may be called upon to act as a high efficiency switch to completely enable or disable power dissipation by the complex load (0103). It is extremely important that this switching function be electrically efficient, meaning that the xe2x80x9conxe2x80x9d impedance magnitude of the switch be near zero ohms. It is significant to note that it is the impedance magnitude and not just the DC resistance value of the switch that is of importance here. Thus, the parasitics associated with the voltage regulator/switch module, including parasitic xe2x80x9conxe2x80x9d resistance, capacitance, and inductance are of concern in these designs, especially with highly dynamic complex loads (0103) as occur in a microprocessor or any analog/digital integrated circuit environment.
One method employed by the prior art and which has been useful in some implementations is the use of a multi-value supply voltage topology as illustrated in FIG. 2. Here, the system supply voltage is maintained at +5V, and used to supply both the 3.3V system regulator as well as the I/O circuitry. In this manner, the internal digital core voltages can be maintained at low voltage levels to prevent oxide punchthrough and other reliability problems, while permitting the circuit to be integrated with other +5V parts. See Gerrit W. den Besten and Bram Nauta, xe2x80x9cEmbedded 5V-to-3.3V Voltage Regulator for Supplying Digital IC""s in 3.3V CMOS Technologyxe2x80x9d, IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 33, NO. 7, at 956-962 (July 1998).
Note that any use of this technique dictates that level shifter circuitry be implemented to interface the lower internal core voltages to the higher interface voltages that are present outside the target integrated circuit. See Nobuaki Otsuka and Mark A. Horowitz, xe2x80x9cCircuit Techniques for 1.5-V Power Supply Flash Memoryxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 32, No. 8, at 1217-1230. A significant issue in all of these level shifting methodologies deals with the capabilities (or lack thereof) in the core integrated circuit fabrication process to handle the elevated voltages present outside the target integrated circuit. Thus, although a level shifting circuit suitable for the interface to the outside world can be fabricated, there still remain issues of reliability in that the higher outside voltages may stress oxides and devices in the level shifting circuitry and thus degrade the overall performance of the system.
While this technique is in general useful in designing modern integrated circuits, there still exist significant practical implementation issues in creating an efficient voltage regulator design within an integrated circuit context. As will be shown later in this document, existing methods to implement efficient regulator schemes are not at present economically scalable to provide the required circuit performance for modern and future integrated microprocessor designs. What is desperately needed both now and in the future is a new regulation/switching technology to address these efficiency issues.
It is instructive before describing the present invention to inspect the methods by which the prior art has addressed the issue of both the regulator and switching functions described previously. This discussion is provided in greater detail in the literature. See Gerrit W. den Besten and Bram Nauta, xe2x80x9cEmbedded 5V-to-3.3V Voltage Regulator for Supplying Digital IC""s in 3.3V CMOS Technologyxe2x80x9d, IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 33, NO. 7, at 956-962 (July 1998).
A Note Concerning MOSFET Strength
The following discussion will make use of the term xe2x80x98MOSFET strengthxe2x80x99 which concerns the transconductance characteristics of a MOSFET that are directly related to the geometry of the device. In general, the transconductance (gm) of a MOSFET will be given by the relation       g    m    ∝      W    L  xe2x80x83A≅Wxc3x97Lxe2x80x83xe2x80x83(1)
where
Axe2x89xa1effective chip area consumed by MOSFET (microns2)
Lxe2x89xa1effective gate length of the MOSFET (microns)
Wxe2x89xa1effective gate width of the MOSFET (microns)
It is significant to note that the device length (L) is limited by the process technology and applied supply voltage, so to achieve a certain device current passing capability, there must be a corresponding increase in the area (A) consumed by the MOSFET.
Similar tradeoffs occur for every type of active device: to pass a given amount of current (with a specified series resistance typically referred to as RDS(on)) requires a minimum amount of area that is technology dependent. The xe2x80x98strengthxe2x80x99 of the device is therefore dictated by the application requirements, and this in turn indirectly dictates the size of any MOSFET or other active device used to pass the current. The significance of this minimum area requirement will be revisited throughout this document in a variety of contexts.
PMOS Pass Device (0300)
Referencing FIG. 3, a common method of providing voltage regulation is to use an operational transconductance amplifier (OTA) in conjunction with a strong P-channel MOSFET (0301) in a negative feedback arrangement. The literature indicates that while the OTA provides sufficient feedback to ensure that the output voltage remains constant, the circuit suffers from an increase in output impedance with increasing dynamic loading frequency. This is undesirable in a digitally clocked system where high frequency current spikes will be present at the drain of the pass MOSFET device (0301).
As with all systems of this configuration, the Miller capacitance associated with this device is multiplied by the transconductance gain of the pass device, making the frequency rolloff larger as the size of the pass MOSFET device (0301) is increased. Thus, as the current carrying capacity demands of the output load are increased, requiring a stronger (higher W/L ratio) in the pass MOSFET device (0301), the high frequency response of the system actually decreases further, an undesirable result.
It is significant to note that the literature mentions that this high frequency rolloff characteristic may be mitigated by the use of a large output capacitor Cext (0302, 0402, 0502). However, the drawback of this additional component is one of the use of additional chip area for its fabrication. This is unfortunate, but a necessary evil of this design topology. While the literature has mentioned some means to reduce the power consumption associated with the output capacitance as exemplified by the schematic of FIG. 6, the high frequency rolloff characteristic is a fundamental design constraint that limits the performance of the regulator/switch. See Gabriel A. Rincon-Mora and Phillip E. Allen, xe2x80x9cA Low-Voltage, Low Quiescent Current, Low Drop-Out Regulatorxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 33, No. 1, at 36-44 (January 1998).
NMOS Source Follower (0400)
Referencing FIG. 4, this configuration appears to be identical to that of FIG. 3, but the difference here is that the OTA is used with a N-channel MOSFET in a source follower configuration. Note that this configuration has excellent incremental impedance, as the impedance looking into the pass MOSFET device (0401) from the load is given by the relation                                           r                          o              ⁡                              (                s                )                                              ∝                      1                          g              m                                      =                  L          W                                    (        2        )            
where
ro(s)xe2x89xa1effective incremental impedance looking into MOSFET source
Here it is significant to note that the stronger (larger) the pass MOSFET device (0401) is constructed, the stiffer the supply regulation becomes. This is a desirable characteristic, but comes with the penalty that the regulated output voltage must be one threshold voltage (VTH) below the VDDD supply rail.
NMOS Source Follower with Charae Pump (0500)
The literature has attacked the deficiencies of the circuit topology of FIG. 4 by incorporating a charge pump into the design as illustrated in FIG. 5. Here the charge pump permits the gate voltage of the pass MOSFET device (0501) to exceed that of the VDDD supply, making it possible to drive the regulated output voltage all the way to the level of the VDDD supply voltage.
Power Conversion Charge Pump Methodology
Often it is necessary in integrated circuit design to generate a high internal voltage supply for use within the confines of the target integrated circuit. These designs invariably use a capacitor-based charge-pump approach to provide the required power conversion. Applications for this methodology include flash memories and bias generators for DRAM memory systems. See Takayuki Kawahara, Syun-ichi Saeki, Yusuke Jyouno, Naoki Miyamoto, Takashi Kobayashi, and Katsutka Kimura, xe2x80x9cInternal Voltage Generator for Low Voltage, Quarter-Micrometer Flash Memoriesxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 33, No. 1, at 126-132 (January 1998).
However, it should be noted in all these prior art examples, there is in general only a small power conversion requirement dictated by the application. That is, the current demands on the converted power supply are minimal. Thus, this technique is of less use in regulating large power supply voltages to smaller voltages for use with low voltage target integrated circuit systems.
Circuit Integration (0600)
As illustrate in FIG. 6, any of the approaches of FIGS. 3-5 may be utilized with a scaled feedback scheme to sense the regulated output voltage at some level lower than the actual regulated output voltage. This technique may be utilized with conventional bandgap references as well as replication of the output driver structure to achieve better voltage stability at the complex load as described in the literature. See Gerrit W. den Besten and Bram Nauta, xe2x80x9cEmbedded 5V-to-3.3V Voltage Regulator for Supplying Digital IC""s in 3.3V CMOS Technologyxe2x80x9d, IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 33, NO. 7, at 956-962 (July 1998).
Summary
It should be noted that in all the schemes mentioned above, the performance of the pass MOSFET transistor and the size of the required filter capacitor are key performance considerations in any of these designs. To perform well under high frequency dynamic loading conditions, the designs above must all have significant filtering capacitance and the impedance characteristics of the pass MOSFET transistor must be designed for low dynamic transconductance.
Relating Pass Device Strength and Capacitance
The need for improved voltage/current regulation/switching within the context of an integrated circuit environment is not a new problem. Engineers have essentially addressed this problem by using larger integrated capacitors for filtering and have increased the strength (and corresponding area) of the pass MOSFET transistor to accommodate the increased dynamic loading characteristics of modern microprocessors and other mixed-signal integrated circuits.
It is helpful at this point to quote the literature regarding the rationale behind this design philosophy. Gerrit W. den Besten and Bram Nauta as referenced above have stated that
xe2x80x9cThe circuit part consisting of C1 [0302, 0402, 0502] and M1 [0301, 0401, 0501] consumes most of the die area of the complete voltage regulator. One can either spend a lot of area on C1 or on M1. If C1 is made very large, then the ripple on VG will be small; the Vgs variation may then be 400 mV, and M1 need not to be too large. On the other hand, if C1 is made small, then the VG variation will be large. This means that the is less left for Vgs variation, and thus M1 becomes large. The optimization has been done numerically, which led to an optimal ratio between capacitor and transistor area.xe2x80x9d
It is significant to note in this cited circuit application that the design required a 3xcexa9 impedance for M1 (0301, 0401, 0501) as the pass MOSFET device, which yielded the desired regulated voltage variation of +300 mV with a peak power supply load of 100 mA. To achieve this design requirement, the W/L of M1 was sized at 14000 xcexcm/0.5 xcexcm for a total device area of at least 7000 xcexcm2. Assuming that C1 was equally as large, the total area (A) consumed by the regulator was on the order of 14000 xcexcm2, or approximately 140000 xcexcm2/A of regulated output current.
Limits to Low Power Operation
Even if the desired pass device could be properly constructed as indicated above, there remains a serious performance issue of parasitic capacitance associated with a pass device fabricated with this amount of die area. As stated by the literature,
xe2x80x9c . . . current efficiency plays a pivotal role in designing battery-powered supplies. The two performance specifications that predominantly limit the current efficiency of low drop-out regulators are maximum load-current and transient output voltage variation requirements. Typically, more quiescent current flow is necessary for improved performance in these areas.
Output current and input voltage range directly affect the characteristics of the pass element in the regulator, which defines the current requirements of the error amplifier. As the maximum load-current specification increases, the size of the pass device necessarily increases. Consequently, the amplifier""s load capacitance (Cpar [0302, 0402, 0502]) increases. This affects the circuit""s frequency performance by reducing the value of the parasitic pole present at the output of the amplifier. Therefore, phase-margin degrades and stability may be reduced accordingly. As a result, more current in the buffer stage of the amplifier is required, be it a voltage follower or a more complicated circuit architecture. In a similar manner, low input voltages require that MOS pass device structures increase in size and thus yield the same negative effects on frequency response and quiescent current as just described. This is because the gate drive decreases as the input voltages decrease, thereby demanding larger MOS pass elements to drive high output currents.
Further limits to low quiescent current arise from the transient requirements of the regulator, namely, the permissible output voltage variation in response to a maximum load-current step swing. The output voltage variation is determined by the response time of the [regulator] circuit, the specified load-current, and the output capacitor. The worst case response time corresponds to the maximum output voltage variation. This time limitation is determined by the closed-loop bandwidth of the system and the output slew-rate current of the error amplifier. These characteristic requirements become more difficult to realize as the size of the parasitic capacitor at the output of the amplifier (Cpar) increases, which results from low-voltage operation and/or increased output current specification. Consequently, the quiescent current of the amplifier""s gain stage is limited by a bandwidth minimum while the quiescent current of the amplifier""s buffer state is limited by the slew-rate current required to drive Cpar.xe2x80x9d
See Gabriel A. Rincon-Mora and Phillip E. Allen, xe2x80x9cA Low-Voltage, Low Quiescent Current, Low Drop-Out Regulatorxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 33, No. 1, at 36-44 (January 1998). This quote validates the premise that increased capacitance comes at the penalty of increased power dissipation, whether static or dynamic.
Scalability (0700)
Another significant problem with the design approach as detailed above is its lack of scalability to the high current levels that are and will be experienced by advanced digital and analog integrated circuitry. Referencing FIG. 7, it is well known in the industry that there is an exponential relationship between the size of an integrated circuit and its cost. While various literature describes the cost as proportional to some exponential function of the chip die area (See Mark Dorais, xe2x80x9cAnalyze ASIC Designs To Optimize Integration Levelsxe2x80x9d, supplement to ELECTRONIC DESIGN, at 83-86 (Aug. 9, 1999)), others have more rigorously quantified this relationship to be cubic, meaning that the cost of a given integrated circuit chip is generally proportional to the cube of the die area (See John L. Hennessy and David A. Patterson, COMPUTER ARCHITECTURExe2x80x94A QUANTITATIVE APPROACH, at 60 (ISBN 1-55880-069-8, 1990)). 
Die Size Considerations
In any case, using the data illustrated in FIG. 7, the chip die for the Gerrit W. den Besten and Bram Nauta reference would put their disclosed chip design die cost approximately at point (0701) (14000 xcexcm2=0.014 mm2) in FIG. 7. Now the question arises as to what happens if the peak current requirements are raised from 100 mA as in the Gerrit W. den Besten and Bram Nauta reference to that of modern or future microprocessors. Specifically, it should be noted that the advent of low voltage processors (xe2x89xa61.0V to 1.8V VDD) with corresponding high current transients (50A to xe2x89xa7100A) will require that any power supply used to support these regulators be capable of xe2x80x9cdeal[ing] with very dynamic loads at high current-slew rates during transients.xe2x80x9d See Roger Allan, xe2x80x9cLateral CMOS Process Yields 7.4V MOSFET With An On-Resistance of 6 mxcexa9xe2x80x9d, ELECTRONICS DESIGN 36-37 (Jul. 12, 1999).
According to the rough calculations done previously indicating that the effective die area needed for a given ampere of regulated output current would be on the order of 140000 xcexcm2/A, a 100 A regulation scheme would require a chip die area of 14000000 xcexcm2=14 mm2 which roughly corresponds to point (0702) in FIG. 7. This calculation is verified by Gerrit W. den Besten and Bram Nauta which state that
xe2x80x9c[a]bsolute values of M1 [0301, 0401, 0501] and C1 [0302, 0402, 0502] depend on the peak load current to be expected. If N times more current is needed, C1 and M1 become a factor of N larger. Since the area of the regulator is dominated by M1 and C1, its area is proportional to the expected peak load current.xe2x80x9d
Using this rough graphical estimate, it can be seen that the chip die cost for the 100 A regulator will be at least 20-30 times that of the 100 mA regulator configuration. Thus, while the die area may be made linear to the required output load current, the nonlinear nature of the die cost to die area dictates the total die cost when all factors are considered simultaneously. This is a significant scaling penalty, and it should be noted that the heat dissipation problems and reliability problems associated with the current concentrations in this topology have yet to be addressed by the prior art. It is therefore doubtful that this design approach will be of significant use in working with future highly integrated microprocessor systems and other mixed signal system integrations.
Gate Drive Limitations
Another significant issue not accounted for in the den Besten analysis for future product designs is the impact of reduced gate drive on the ability to generate pass devices with sufficiently low RDS(on) values. Recall that the drain resistance of a MOSFET operating in the saturation region (with VGS greater than VT; VDS greater than VGSxe2x88x92VT) is given by the first-order relation                                                                         R                                  DS                  ⁡                                      (                    ON                    )                                                              =                                                2                  β                                ⁢                                  1                                                                                    [                                                                              V                            GS                                                    -                                                      V                            T                                                                          ]                                            2                                        ⁢                    λ                                                                                                                          =                                                2                                      K                    xe2x80x2                                                  ⁢                                  L                  W                                ⁢                                  1                                                                                    [                                                                              V                            GS                                                    -                                                      V                            T                                                                          ]                                            2                                        ⁢                    λ                                                                                                          (        3        )            
Noting that the den Besten analysis assumed a 3.3V, and assuming comparable threshold voltages (VT) of 0.6V, it can be seen that the gate drive component of the den Besten system is approximately 1.0/(3.3xe2x88x920.6)2=0.137. If the system is now converted to a 1.5V process with all other factors equal, the gate drive becomes 1.0/(1.5xe2x88x920.6)2=1.235, or approximately an order of magnitude greater than the 3.3V system.
This gate drive component is important in the analysis because as the maximum process voltage decreases, the threshold voltages cannot be decreased at will without incurring higher leakage losses (and increased power consumption) in the system. Therefore, the resulting increase in RDS(on) resistance due to reductions in gate drive in many circumstances requires that the size of pass devices be increased to compensate for the effective decrease in drive strength of the pass MOSFET device. Incorporating this additional factor of 10 into the calculations for a 100 A pass device as described above would increase the overall device size to 1400000 xcexcm2/A, or a total chip die area of 140000000 xcexcm2=140 mm2. This would clearly make this solution uneconomical in most integrated circuit system designs.
Metalization Distribution Limitations
One aspect of the current art that has become a significant limitation in the generation of modern large integrated circuit systems deals with losses associated with metalization distribution. This problem is best illustrated graphically as in FIG. 16. Here an integrated circuit system is depicted (1600) having a variety of analog (1611, 1613) and digital (1612) systems on the same chip. Bond pads (1601, 1602) are used to supply VSS and VDD power connections respectively.
The problem typically encountered in such systems is a tradeoff between area efficiency in distributing power and power supply noise integrity. Referencing the VSS pad (1601) tree-style bus routing, it can be seen that the voltage drop incurred along the common VSS bus by the digital (1612) and analog (1613) systems is impressed on the bus before it reaches the first analog system (1611), causing a voltage drop and corresponding noise injection into this circuit.
Integrated circuit layout designers have typically abandoned tree-style bus routing in modern integrated circuit layout for the single-point bus routing that is illustrated on the VDD bond pad (1602). Here there are individual power bus traces being routed to each of the analog/digital subsystems (1611, 1612, 1613), and thus the common voltage reference point is (1602). Voltage drops incurred by the load generated by each subsystem are in part limited to the power supply of that subsystem. Note that due to finite bond wire inductance there will always be some noise induced at the bond pad (1602) due to transients in the power consumption of the analog/digital subsystems (1611, 1612, 1613). While this technique can be of great use in many mixed signal circuit designs, it does not solve all the problems that can occur in modern high-speed integrated circuit design.
The main problem is that the metalization routing illustrated in either technique of FIG. 16 produces only a passive regulation, using the inherent metalization resistance to perform the required noise isolation between the systems. Even if the metalization were to cover the entire top of the chip, there would still be significant noise coupling between individual circuit components. This requirement is more pronounced with increasing current demands on the entire integrated circuit system.
While some techniques have been developed to stack wafers on top of one another using xe2x80x98bumpxe2x80x99 or xe2x80x98ballxe2x80x99 technologies as illustrated in FIG. 27, these have proven difficult and expensive to use for commodity integrated circuit applications. In general, these techniques will not become economically feasible until the tooling for these designs overcomes some basic reliability problems associated with the mechanical assembly process inherent in any chip stacking procedure.
What is needed in the industry at the present and in future designs is an active regulation and noise reduction scheme. To date nothing in the prior art has suggested how this might be accomplished, but the present invention does provide a useful method to implement this functionality at a general and very broadly applicable level.
Other Considerations
It must be additionally noted that irrespective of the resulting die cost, the addition of 14 mm2 die area to any existing high complexity integrated circuit design severely dictates what package styles will be available for use with the product. Only the largest of ceramic packages can afford to incorporate an additional half-inch square die just for local power regulation purposes. Thus, there are significant mechanical considerations to the addition of any pass/regulation device consuming this amount of die area.
In the interim, as exemplified by the MOSFET structure illustrated in FIG. 8, there have been some approaches to solving the problem described above in that some researchers have utilized multiple metal levels and interdigitated drain/source strapping to minimize the effective impedance of the drain/source channel in a conventional MOSFET. A recent MOSFET configuration using this approach has been reported in the literature. See Roger Allan, xe2x80x9cLateral CMOS Process Yields 7.4V MOSFET With An On-Resistance of 6 mxcexa9xe2x80x9d, ELECTRONICS DESIGN 36-37 (Jul. 12, 1999).
However, even this approach has its drawbacks. Allan reports that the effective drain-source resistance for a typical interdigitated MOSFET configuration is given by the relation                                                                         R                EFF                            =                              xe2x80x83                            ⁢                                                                                          rR                                        ⁢                                          coth                      ⁡                                              (                                                  N                          ⁢                                                                                    r                              R                                                                                                      )                                                                              +                  rc                                2                                                                                        ≅                              xe2x80x83                            ⁢                                                                                          rR                                        +                    rc                                    2                                ⁢                                  xe2x80x83                                ⁢                for                ⁢                                  xe2x80x83                                ⁢                large                ⁢                                  xe2x80x83                                ⁢                N                                                                        (        4        )            
where
Rxe2x89xa1RON(simulated)+RCONTACT 
rxe2x89xa1resistance of the metal trace between a two-unit cell
rcxe2x89xa1resistance of the metal trace between drain and source pads
Nxe2x89xa1number of devices integrated
What is significant to note from this relation is that the overall drain-source resistance is not significantly decreased beyond a given limit. So, the basic performance of the lateral MOSFETs utilized in this interdigitated scheme cannot be significantly improved by virtue of this topology. Therefore, the resulting chip die area for very large current carrying pass devices is still considerable, yielding an unacceptable (yet marginally better) die cost and resulting lowered die yield and reliability.
What is also absent from the analysis reported by Allan is the cost/yield impact of adding the interdigitated metalization layers to an existing design. While the cost of extra metal layers has continuously dropped with time, the extra processing steps involved in the Allan methodology has yet to prove economically viable given current technology. Additionally, as indicated in the title of the article, the structure reported by Allan is essentially a low-voltage (7.4V) MOSFET, and not suitable for even 12V automotive applications, and clearly not applicable for high voltage applications.
Finally, an unmentioned and unresolved issue in the configuration reported by Allan is that of thermal management. The pass devices created using this methodology must by their very nature be placed at some portion of the subject integrated circuit. The high power density being passed by this pass device tends to locally increase the temperature on the integrated circuit, and generate a thermal gradient across the integrated circuit die. This thermal gradient makes integration of precision analog circuitry difficult, and presents significant reliability and performance issues with remaining digital circuitry. Neither the structure reported by Allan nor the prior art solves this thermal gradient problem.
Overview
While linear regulation schemes as illustrated in FIGS. 3-6 have been widely used within the electronics industry for decades, the advent of personal computer (PC) systems has driven a move in most new designs to switched-mode regulators that are essentially DC-DC power converters having a regulated output voltage. These systems are often characterized in the art as xe2x80x98boostxe2x80x99, xe2x80x98buckxe2x80x99, or xe2x80x98buck/boostxe2x80x99 converters to describe their capability to take a given DC input voltage and increase, decrease, or increase/decrease it respectively to generate a regulated output voltage.
These systems have traditionally used one or more external power switches to perform the buck/boost functionality within the context of the switching regulator. This may be seen by inspecting the placement of Q1, Q2, and Q3 in FIG. 13 and FIG. 15. In both circumstances the energy storage inductor L1 is switched either to either supply rail via use of the gate controls of Q1 and Q2/Q3 respectively.
Integrated Power Switches
Recently switched-mode power supply integrators have moved towards integration of these switches on the same chip as the switched-mode controller integrated circuit. Examples of this integration are illustrated in FIG. 9, FIG. 10, FIG. 11, and FIG. 30. In many of these circumstances the manufacturers are emphasizing the small package size of the overall integrated system containing both the controller and the power switching devices (which are typically fabricated using lateral MOSFET pass devices). However, these integrated versions have some serious drawbacks, including the following:
1. The small package size limits the effective area (A) of the MOSFET pass devices, and as a result the current supplying capability of these designs is severely restricted. Rather than being capable of supplying dozens of amperes of peak current, these integrated pass device implementations are generally limited to low current ( less than 3 A) applications.
2. The use of lateral MOSFETs in these integrated switching power supply controllers dictates both a low breakdown voltage as well as a relatively inefficient transconductance as compared to a wide variety of vertical MOSFET structures.
3. Package lead bond wire resistance can create a significant reduction in the effective Q of the external inductor when operated at high switching frequencies.
4. At high switching frequencies, radiation of RF energy from the switching system is a problem and must be shielded to conform to FCC and other regulatory restrictions.
5. While the integrated switching supply controllers illustrated in FIGS. 9-11 are by themselves small, the addition of the required external components typically doubles or triples the effective PCB area required to implement these functions. Little has been done to reduce this PCB board area overhead in the prior art. Since PCB board area typically costs $1/square inch in modern designs, this additional area translates directly into additional overhead cost in the final product. Furthermore, the lack of full integration of all external components tends to increase the overall cost of the final product, a result that is always undesirable.
6. Although the switching regulators illustrated in FIGS. 9-11 and FIG. 30 may be efficient at power conversion with low current levels, this is not the entire story when the system supports a complex digital integrated circuit load. Since there is always a finite inductance/resistance along PCB traces between the output of the switching regulator and the input to the complex digital integrated circuit load, this additional impedance can have a significant negative impact on the overall supply regulation at the complex digital integrated circuit load. Since the voltage sensing function for the switching regulator can never probe the voltage at the die surface of the complex digital integrated circuit load, there is insufficient information in the feedback loop to permit the switching regulator to properly adjust the output voltage in response to high power demands from the complex load.
7. While there are both systems that provide for inductor-based conversion (FIGS. 9-10, 30) and capacitor-based conversion (FIG. 11), neither has the potential to support peak currents on the order of 100 A that will be required of future power supply systems supporting low voltage digital systems. In short, while these technologies may improve with time, they are fundamentally limited by their architecture when dealing with the problems present in modern digital system power supply regulation.
While this is just a short list of the drawbacks of the prior art, they should alert the reader to the fact that even with recent advances in integration, there appears to be a host of problems in this art area that have yet to be addressed by the electronics industry. The present invention addresses most if not all of these issues and provides a method to overcome the prior art deficiencies while providing significantly better performance and energy economy in the resulting switched-mode power supply system.
Multi-Stage Power Conversion
1-Step Regulation
One method utilized by at least one integrated switched-mode power supply vendor to improve efficiency is the utilization of multi-stage power conversion within the context of an integrated voltage regulator system. As illustrated in FIG. 12, the performance of a typical 1-step switched mode regulator varies based on the VDDD(IN) supply voltage that is presented to the switched mode regulator system. Based on the curves of FIG. 13, it would appear that using the switched-mode topology in this example (illustrated by the schematic of FIG. 14), the performance of the system increases with decreasing VDDD(IN) supply voltage (lower power lost=higher efficiency for a given load current). The reason for this loss in efficiency is given in the literature:
xe2x80x9cTraditionally, portable CPU voltage regulators operate over a wide range of input voltages. This 1-step regulation technique forces the power supply to operate from battery voltages as low as 8V to adapter voltages as high as 24V. This large input voltage range forces the designer to use a relatively large inductance value for the switch inductor [L1, FIG. 14]. The large inductor value means more energy storage, so the overvoltage transient will be larger with the load current rapidly changes from high to low. Additional output capacitances may be require to meet transient specifications.
CPU core voltage are currently in the 1.5V region. Using the 1-step approach, regulating 24V down to 1.5V forces the regulator to regulate narrow xe2x80x98sliversxe2x80x99 of input current to meet the transient requirements of high speed CPUs. A 24V wall adapter forces a 6.25% duty cycle when supplying a CPU voltage of 1.5V which means that the top [Q1, FIG. 14] MOSFET conducts for 0.2 us each cycle, at 300 kHz.xe2x80x9d
See John Seago, Linear Technology Design Note 209, xe2x80x9c2-Step Voltage Regulation Improves Performance and Decreases CPU Temperature in Portable Applicationsxe2x80x9d, www.linear-tech.com/go/dnLTC1736 (August, 1999). While this loss of efficiency is a problem with 1-step regulation schemes, they are far more common than 2-step regulation schemes in common system designs.
2-Step Regulation
In contrast to 1-step regulation, the power lost using 2-step regulation can in low load current circumstances be made less than a 1-step regulator as illustrated in FIG. 14. Contrast the circuit topologies of FIG. 13 and FIG. 15 and details (1301) and (1501) to illustrate the circuit topology differences between a 1-step and 2-step regulator methodology respectively. Contrasting the performance curves of FIG. 12 and FIG. 14 reveals the fact that operation at a fixed input voltage of 5V proves to be overall more efficient than the 1-step regulator approach for all supply voltages once regulated down to 5V. This might give the reader pause, given that the individual efficiencies of each state of a 2-stage regulator must be less than 100%. The literature explains this anomaly by stating that
xe2x80x9c[a] common misconception is that the total efficiency of two circuits in series is the product of the efficiencies of each circuit. This is not true. Efficiency is defined as the total output power divided by the sum of the total output power plus all circuit losses.
2-step regulation takes advantage of the 5V regulator efficiency curve. The 5V supply has a peak efficiency of about 95% which is relatively flat over a wide range of load currents. The added current required to power the CPU supply causes the 5V regulator efficiency to decrease by about 1% but it also regulates the majority of the CPU power at about 94% efficiency. With a 5V input, the CPU regulator peaks at about 90% efficiency. Comparing 1-step and 2-step conversion efficiencies with a 12V input, the increased loss in the 5V regulator is about the same as the decreased loss in the CPU regulator so the overall system efficiency remains nearly constant.xe2x80x9d
See John Seago, Linear Technology Design Note 209, xe2x80x9c2-Step Voltage Regulation Improves Performance and Decreases CPU Temperature in Portable Applicationsxe2x80x9d, www.linear-tech.com/go/dnLTC1736 (August, 1999).
However, it must be noted that neither of these 1-step or 2-step approaches really tackles the real problem with power conversion in a battery-powered environment: that of parasitic losses in inductors, capacitors, interconnect, and pass devices. The present invention specifically addresses these issues individually and en masse in an attempt to create switching regulator systems that exceed the 90% efficiency standard set by these existing switched mode regulation systems.
Efficiency/Startup Characteristics
As illustrated in FIG. 28, the prior art typically experiences 60-80% power conversion efficiencies for designs that are fully integrated. This poor performance (as compared to 90+% efficiencies with designs utilizing external MOSFET switches) is inherently due to poor on-resistance of the lateral on-chip MOSFETs utilized in current fully integrated designs.
It should be noted that the on-resistance characteristics also dictate a higher starting voltage for systems when the load presented to the regulator is increased. As illustrated in FIG. 29, this minimum starting operating voltage can increase substantially when the load presented to the regulator is increased. This effectively reduces the useful battery life of a portable system, an undesirable characteristic. By reducing the on-resistance of switching devices used in regulators, the present invention overcomes this deficiency in the prior art and improves the capability of systems to operate at depressed battery voltages.
Cascading Area Penalty
It is significant to note in FIG. 13 and FIG. 15 that the transistors (Q1, Q2, Q3) that are driven externally by the integrated circuit must be provide sufficient gate drive to overcome capacitive effects of the large gate plate associated with these transistors. This is especially true in situations where the transistors are integrated as lateral devices on-chip as illustrated in FIGS. 9-11.
This gate drive requirement has associated with it a cascading area penalty to minimize power dissipation during switching of the power transistor. The literature describes this penalty in terms of determining the minimum power dissipation when the transistor size ratio of the final inverter stage to the first stage is given. As stated by the literature (and edited for content herein):
xe2x80x9cThis problem can be seen not only in the DC-DC converter but also in an output pad where the output transistor size is given from specifications such as drive capability.
Power dissipation in the jth stage can be expressed as follows:
P[j]=PC[j]+PS[j]xe2x80x83xe2x80x83(5)
xe2x80x83Where PC[j] is power dissipation due to charging and discharging and PS[j] is power dissipation due to crowbar current. Let us assume that PC[j] is proportional to W[j] and inversely proportional to signal slope. Let us also assume that the signal slope is proportional to W[jxe2x88x921]/W[j] because driving current is proportional to W[jxe2x88x921] and loading capacitance is proportional to W[j]. Then PC[j] and PARTNERSHIP[j] are given by
Pc[j]=Uxc3x97W[j]                                          P            S                    ⁡                      [            j            ]                          =                  V          xc3x97                      W            ⁡                          [              j              ]                                xc3x97                                    W              ⁡                              [                j                ]                                                    W              ⁡                              [                                  j                  -                  1                                ]                                                                        (        6        )            
Where U and V are constants. Total power dissipation is therefore given by
PTOTAL=xcexa3P[j]                                                                        P                Total                            =                              ∑                                  P                  ⁡                                      [                    j                    ]                                                                                                                          =                                                V                  ⁡                                      (                                          M                      -                      1                                        )                                                  xc3x97                                                      x                    ⁡                                          (                                              K                        +                        x                                            )                                                                            x                    -                    1                                                  xc3x97                                  W                  ⁡                                      [                    0                    ]                                                                                                          (        7        )            
where                                           x            =                                          W                ⁡                                  [                  j                  ]                                                            W                ⁡                                  [                                      j                    -                    1                                    ]                                                              ⁢                      
                    ⁢                      M            =                                          W                ⁡                                  [                  n                  ]                                                            W                ⁡                                  [                  0                  ]                                                              ⁢                      
                    ⁢                      k            =                          U              V                                      ⁢                  
                                    (        8        )            
When the partial derivative of Ptotal/x is zero the total power dissipation becomes minimum. Then                               x          =                      1            +                                          1                +                K                                                    ⁢                  
                ⁢                  N          =                                    ln              ⁡                              (                                                      W                    ⁡                                          [                      n                      ]                                                                            W                    ⁡                                          [                      0                      ]                                                                      )                                                    ln              ⁢                              xe2x80x83                            ⁢              x                                                          (        9        )            
. . . xe2x80x9d See Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, and Tohru Furuyama, xe2x80x9cVariable Supply-voltage Scheme for Low-Power High-Speed CMOS Digital Designxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 33, No. 3, at 454-462 (March 1998).
What is significant about equation (9) is that the number of stages (N) is generally proportional to the natural logarithm of the size ratio between the smallest integrated driver and the size of the largest (possibly non-integrated) driver. If these ratios are large, the number of buffer stages can be significant, and result in a substantial loss of integrated circuit die area in the fabrication of these devices. Note that this formulation is generally applicable to lateral MOSFET devices, and would be improved somewhat when using Chen-style devices (or other vertical pass devices) that have substantially lower gate capacitances than their lateral counterparts. This capacitance differential is used to advantage in the present invention.
In summary, while the prior art has endeavored to improve both linear and switched-mode regulator systems for use with complex integrated circuit loads, there appears to be a host of practical issues that have yet to be addressed, including but not limited to the following:
1. RDS(on) values for linear regulator systems are still too high to solve problems with high current digital systems.
2. Associated capacitance requirements for linear regulators are too high to provide for fast response to high-current step loads.
3. Integration levels and power handling capabilities of switched mode regulators are too low for many modern digital systems.
4. Existing linear and switched mode regulators are generally not low power if they must supply a high current output load.
5. The economics of extrapolating the current design techniques for on-chip power supply regulation are cost prohibitive.
6. Gate drive limitations for low voltage systems dictate that pass device areas be so huge so as to be uneconomical in many circumstances using existing design techniques.
7. Proposed xe2x80x98novelxe2x80x99 MOSFET topologies in the literature are not amenable to high voltage environments, such as might be present in an all-electric automobile or in a household appliance.
8. Thermal management in the prior art is problematic because of the slavish use of lateral MOSFETs in these designs. This mantra has been taken for granted within the prior art, as existing process techniques did not provide for the economic integration of both vertical power devices and high-density digital control logic.
These points taken individually may in some rare cases be solvable by niches of the prior art, but combinations of these problems are the norm in modern integrated system design, and such combinations have proven intractable via use of existing design methodologies. The industry is primed for a system/method whereby these drawbacks in the current art can be overcome and thus provide a platform for the next generation of high performance fully integrated digital/analog systems.
Accordingly, the objects of the present invention are (among others) to circumvent the deficiencies in the prior art and affect one or more of the following objectives:
1. Significantly improve the RDS(on) characteristic of pass devices used in conventional regulator/switch functions in an integrated circuit environment.
2. Improve the performance of regulator/switch functions within an integrated circuit environment by permitting the use of lateral and/or vertical pass devices in these circuits.
3. Reduce or eliminate the amount of circuit chip die area that is consumed by pass devices in regulator/switch functions to improve the overall cost of integrated circuits requiring these functions.
4. Permit high voltage pass devices to be incorporated on the same integrated circuit die as low voltage circuitry without the need for exotic fabrication processes.
5. Permit integration of analog and digital systems on the same chip with minimal noise and crosstalk between the systems.
6. Permit independent regulation/switching of voltage/current/power to various portions of a given integrated circuit so as to allow both better PSRR for each system component as well as the option of reducing overall system power by switching off various integrated circuit subsystems when not in use.
7. Provide an economical and efficient means for digital integrated circuits that are targeted towards portable applications to manage power consumption so as to conserve battery power and extend battery life in these applications.
8. Permit retrofit of existing integrated circuits to permit incorporation of improved regulator/switching capabilities.
9. Improve the local power supply stability in a wide variety of integrated circuits as compared to the prior art.
10. Permit the integration of high current regulator/switch functions in modern analog, digital, and mixed-signal designs.
11. Permit the use of integrated appliance system networks in areas that heretofore were not practical due to lack of integration in the prior art.
While these objectives should not be understood to limit the teachings of the present invention, in general these objectives are achieved by the disclosed invention that is discussed in the following sections.
Briefly, the invention is a system and method permitting voltage and/or current regulation and/or switching of power within the context of an integrated circuit environment while simultaneously eliminating the need for chip area consumption by high current capacity pass devices commonly employed within the prior art. Rather than implementing the required pass devices necessary for voltage/current regulation/switching on the same integrated circuit plane as the foundation integrated circuit (FIC), the present invention implements the regulator/switching structure on top (or bottom) of the existing foundation integrated circuit. Thus, as illustrated in FIG. 17, the term foundation integrated circuit will be used to describe the existing integrated circuit xe2x80x98foundationxe2x80x99 on which the regulator/switch functionality is fabricated.
This new regulator/switching topology can make use of a wide variety of pass transconductor types, but many preferred embodiments of the present invention utilize Chen-style vertical MOSFETs (as described in U.S. Pat. No. 5,216,275) or the like to provide for superior RDS(on) performance and corresponding xe2x80x98stifferxe2x80x99 supply regulation characteristics. While the present invention topologies are applicable to both regulator and/or switching applications, there is a particular class of applications involving high speed low voltage microprocessors in which the present invention excels over the prior art. Specifically, the advent of low voltage processors (xe2x89xa61.0V to 1.8V VDD) with corresponding high current transients (50 A to xe2x89xa7100 A) will require that any power supply used to support these regulators be capable of xe2x80x9cdeal[ing] with very dynamic loads at high current-slew rates during transients.xe2x80x9d See Roger Allan, xe2x80x9cLateral CMOS Process Yields 7.4V MOSFET With An On-Resistance of 6 mxcexa9xe2x80x9d, ELECTRONICS DESIGN 36-37 (Jul. 12, 1999).
The present invention solves the problems present in the prior art by permitting the following:
1. Pass devices generated using the present invention may be of the vertical device configuration (a feature not possible with the prior art), permitting drastically reduced RDS(on) resistance values as compared to conventional lateral MOSFET and BJT device structures. Thus, it is easy to fabricate pass devices with RDS(on) resistance values approaching three orders of magnitude lower than conventional lateral device geometries.
2. No additional chip area is necessary to implement voltage and/or current and/or power regulation and/or switching functions, in contrast to the prior art that requires large chip area sacrifices to implement any form of regulation and/or switching functions.
3. Since no additional chip area is necessary to implement pass devices using the present invention, the pass devices utilized for regulation/switching functions are only limited by the die area of the foundation (bottom/top) integrated circuit.
4. Since pass devices may have large effective areas in the present invention without consuming additional foundation chip area, the quality of the pass device (from a per unit performance perspective) need not be on par with the rest of the process technology to still provide significant advantages over the prior art lateral-type foundation integrated circuit pass devices. Thus, the economics of the present invention are superior to the existing prior art even using low-quality pass devices, as long as the effective performance of the low quality device can overcome the additional area penalty associated with the prior art configurations.
5. Existing integrated circuits may be augmented with voltage regulation/switching functions without the need for massive re-layout of the foundation integrated circuit. Thus, retrofit of existing integrated circuits is entirely possible using the present invention. This feature may be heavily utilized in system-on-a-chip (SOC) designs where existing intellectual property (IP) chip designs are integrated on a single die and independently regulated/switched using the present invention.
6. In contrast to prior art regulation/switching implementations, the present invention requires much less chip layout planning for its implementation. Regulation/switching functions occur at another level of integration and are separate from the routing concerns at the foundation integrated circuit level.
7. The present invention provides a more uniform power plane to the foundation integrated circuit than is possible with existing power routing within prior art integrated circuits. By providing a uniform metalized base plate, the present invention eliminates the need for exotic chip layout methodologies to minimize power supply noise coupling within the foundation integrated circuit. See Mark Ingels and Michiel S. J. Steyaert, xe2x80x9cDesign Strategies and Decoupling Techniques for Reducing the Effects of Electrical Interference in Mixed-Mode ICsxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 32, No. 7, at 1136-1141 (July 1997).
8. While conventional integrated circuit design tends to dictate separate power and ground busses for mixed signal designs, the present invention permits individual regulation of the power supplies for separate parts of a mixed-signal foundation integrated circuit.
9. The ability to provide for individual regulation of power within separate portions of the foundation integrated circuit permits a much more robust PSRR to be achieved than that which is possible with existing integrated circuit layout techniques. This independent regulation capability permits high levels of isolation to occur between analog and digital circuitry on the same chip, thus permitting a higher degree of integration with mixed-signal integrated circuit designs.
10. In contrast to traditional methods of power supply routing within an integrated circuit, the present invention utilizes. a power plane interconnect philosophy similar to that employed in printed circuit board (PCB) manufacturing. This methodology provides for both reduced power supply noise in remote areas of the integrated circuit, but also provides an inherent capacitive charge storage element that tends to stabilize the power supply voltage at the point of use within the foundation integrated circuit. Additionally, since the present invention integrates active devices as part of the power distribution plane, a level of performance and efficiency not possible with conventional PCB designs is possible.
11. By providing a more reliable and stable power source, the present invention increases the reliability of existing digital, analog, and mixed-signal designs above that available in the prior art. Because the voltage fluctuations on the local power supply are drastically reduced as compared with the existing prior art, random external power fluctuations may be more easily filtered by the present invention before they impact the performance of the foundation integrated circuit.
12. The present invention permits higher supply voltages to be utilized to power low voltage analog and/or digital core circuitry without the need for exotic integrated circuit process steps. The reliability problems with conventional circuitry with respect to stressing thin gate oxide are eliminated with the present invention topology. This capability may in some circumstances permit the foundation integrated circuit to be powered from high voltage power sources such as the AC line and/or car and truck batteries, thus eliminating the need for external AC/DC converters and/or regulators.
13. The present invention provides the only known method of supplying peak currents on the order of hundreds of amperes for high density digital and analog designs that are at the forefront of today""s and future growth trends in integrated circuit manufacture.
14. The present invention permits the thermal gradient normally associated with regulator/switch pass devices to be largely eliminated. Since the regulator/pass devices are positioned above/below the foundation integrated circuit which is powered by the pass device, the localized thermal increase is evenly distributed above the circuitry affected, thus permitting precision analog circuitry to be fully integrated in a mixed-signal environment with little concern for errant thermal gradients across the chip.
15. The present invention permits the only known method of incorporating anticipatory regulation within the power regulation methodology structure of an integrated circuit. This form of regulation is proactive, rather than reactive as taught within the prior art, and can in many circumstances provide tighter regulation with less system overhead than required in the prior art.
While the above list is only a partial depiction of the benefits of the present invention, more detail and information is available by inspection of the accompanying drawings and informative text.